1. Field of the Invention
The present invention relates to microprocessors, and more particularly to apparatus for controlling the movement of data off of and onto a microprocessor chip.
2. Description of the Prior Art
Computer systems have in the past been concerned with the movement of digital data between modules in the system. Traditionally, the central processing unit has been packaged separately from memory units and peripheral input/output devices such as disc files, printers, and magnetic tape storage units. Prior to the development of large-scale integration (LSI) technology, the interface between units was mainly concerned with transferring data at the highest speed possible commensurate with the electrical characteristics of the cables between the units and the electronic circuits which drive signals on the cables. An example of such an interface in wide use today is that used on the IBM System/360 computers between input/output devices and the input/output channel of the main processor. This interface is described in U.S. Pat. No. 3,336,582--Interlocked Communication System--Beausoleil et al, filed Sept. 1, 1964, and issued Aug. 15, 1967. This I/O interface provides for a data format and control signal sequence definition which is common to all control units which can be attached to the system. The rise and fall of all signals transmitted over the interface are controlled by corresponding interlocked responses. In such a system there is no practical limit on the number of lines which can be utilized between the units, and, therefore, a separate bus is provided for address information and data information. The width of the data bus is conveniently made equal to the width of data words utilized within the data processing unit. Furthermore, the address bus is made equal to the width of the data word used for address development. The IBM System/360 Interface therefore uses nine lines to represent bus out which is used to transmit data, I/O device addresses, commands, and control orders to the peripheral devices. Furthermore, a separate set of nine lines, bus in, is used to transmit data, selected I/O device identification, status information, and sense data from the peripheral devices. In addition, more than 16 simplex input and output lines are utilized for controlling information on the buses, for special sequences, for the scanning of or selection of attached input/output devices, and for usage meters. A total of over 34 lines are used to control data movement.
The use of such an interface with microprocessors is prohibitive because there are not enough input/output pins available on the LSI package with present-day technology. To solve this problem, microprocessors have to use fewer actual lines interconnecting the modules, but still have the requirement of being able to handle data movement and control operations just as complex as those of previous data processing systems. This has been accomplished in the past by providing bidirectional information bus lines which carry information first in one direction, and then in another direction, thus avoiding duplication of the signal lines. The number of bus lines required is further reduced in prior microprocessors by multiplexing the address of the peripheral device on the data bus and synchronizing the output of both address and data on the output buses. Furthermore, data transfer control signals have been encoded to simplify read and write input/output and memory operations, thus resulting in reduced pin requirements. In addition to a line carrying system clock signals, a typical microprocessor interface would include the following lines:
Two status signal lines are utilized to encode the status of the data transfer, read, write, halt, or fetch. One control line is utilized to indicate whether the device being addressed is a memory device or an I/O device. One line is utilized by an external device to signal a request that the device needs the address and data bus. Another line from the microprocessor indicates to the external device that the abovementioned request has been acknowledged. A separate line is utilized by the peripheral to generate an interrupt request. A single line is utilized by the microprocessor to latch address information into the peripheral device. An 8-bit address bus and a separate 8-bit data bus complete the minimum lines necessary for this type of interface. If a 16-bit address is utilized, the data bus carries a portion of the address word during an address cycle. In a subsequent cycle this bus is used to carry data.
As seen from the above, it takes 23 lines to provide the functions described.
As more and more complex functions are incorporated on a microprocessor chip, the number of pins dedicated to input/output functions becomes more critical. This is particularly true where large microprocessors are partitioned between two or more chips. This means that more and more pins have to be dedicated to interchip control signals, thus making fewer pins available for input/output operations. It is therefore desirable to further reduce the number of bidirectional information bus lines and other pins utilized while maintaining a simplified data transfer protocol between the microprocessor and peripheral units.